A memory-based programmable logic device using look-up table cascade with synchronous static random access memories

A large-scale memory-technology-based programmable logic device (PLD) using LUT (Look-Up Table) cascade is developed in 0.35um Standard CMOS logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) flexible cascade connection structure, 2) multi-phase pseudo-asynchronous operations with synchronous SRAM cores, 3) LUT-bypass redundancy. This chip operates at 33MHz in 8-LUT cascades with 122mW. Benchmark results show that it achieves a comparable performance to FPGAs

Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs

The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs.IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips VIII), April 22-25, 2005, Yokohama, Japa

A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs

2005 International Conference on Solid State Devices and Materials (SSDM 2005), September13-15, 2005, Kobe, Hyogo, Japa

Hardware to Compute Walsh Coefficients

This paper presents a method to compute a fragment of the Walsh coefficients of logic functions using hardware. First, it introduces the Walsh transformation tree, and shows a method to compute Walsh coefficients using the Walsh transformation tree. Next, it shows the hardware realization for the Walsh tree. The amount of hardware to compute a coefficient and the entire coefficients are O(2 ) and O(n ), respectively. FPGA implementations show their feasibility up to n =14. The FPGA realization is at least 1253 times faster than a software implementation on a microprocessor for n =14

An FPGA Design of AES Encryption Circuit With 128-Bit Keys

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. Using the proposed architecture on the Altera Stratix EP1S20F780C5 FPGA, the AES-4SM achieves a throughput of 5.61 Gbps by using 20 M4Ks, and the AES-8SM achieves a throughput of 10.49 Gbps by using 40 M4Ks. Compared with the unrolling implementation that achieves a throughput of 20.48 Gbps by using 80 M4Ks on the same FPGA, implementations with the PPR architecture reduce the amount of memory up to 75% while increasing the memory e#ciency (i.e., throughput divided by the size of memory for core) up to 9.6%. The PPR architecture fills the gap between unrolling and rolling architectures, and fits on less expensive FPGAs

Study for the optimization of the decommissioning project of nuclear facilities

Basically, decommissioning of nuclear facilities is a project that does not generate new profit because it is carried out with the reserve funds from operation, etc. Therefore, its cost should be minimized with optimization by shortening the process and minimizing the waste, etc. Meeting the requirements of exposure risk (safety) also affects the optimization. In this study, we decided to integrate these evaluation methods to develop a comprehensive optimization evaluation method. In this study, we established an average process for the current decommissioning plans of Japanese nuclear power plants and developed a cost evaluation method including sensitivity analysis. As a result of examining the feasibility of the deferred dismantling strategy using the above calculation method, it became clear that although there is a reduction in disposal and dismantling costs due to the natural decay of radioactive materials, the maintenance and management costs during the safe storage period account for a large proportion of the costs, and for this reason, immediate dismantling is unconditionally advantageous, at least in Japan. The components of optimization described above are naturally subject to various uncertainties and risks. For example, there are regulatory risks, and the location of waste disposal site is subject to social acceptance, so there is a great deal of uncertainty. In the future, these factors will be incorporated into the evaluation and studied, and the optimal strategy for decommissioning and what kind of uncertainty should be focused on will be clarified quantitatively

A Design Method for Irredundant Cascades

A realization of multiple-output logic functions using an irredundant cascade is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown

On Designs of Radix Converters Using Arithmetic Decompositions

In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. It introduces a new design technique called arithmetic decomposition. It also compares the amount of hardware and performance of radix converters implemented on FPGAs.